News Article
Thinner Approach To 3-D IC
Applied Materials and DISCO collaborate on wafer thinning technology to enable 3-D semiconductors
Applied Materials. and DISCO Corporation have announced a joint effort to develop wafer thinning processes for fabricating through-silicon vias (TSVs) in 3-dimensional (3-D) semiconductors. The two companies will be working together to develop integrated, high-performance process flows intended to lower the cost, reduce the risk and accelerate time to market for customers' next generation chips.
Through-silicon via technology is a new method that enables higher density, lower-power devices in a smaller footprint by vertically stacking chips. To make this 3-D stack, each chip or wafer layer must be reduced in thickness by up to 90% and bonded to a temporary carrier in order to maintain structural integrity during the thermal and mechanical stresses of semiconductor processing.
Combining DISCO's precision grinding equipment with Applied's etch, dielectric deposition, physical vapor deposition and chemical mechanical planarization systems, the two companies expect to develop wafer thinning and post-thinning processes of wafers bonded to silicon and glass carriers. Some of the key technical requirements in developing manufacturing-worthy equipment and process solutions are wafer structural and edge integrity, handling, dimensional control, particle control, stress management and thermal profile control.
“The alliance of Applied's process integration expertise and our leading wafer thinning systems is great news for chipmakers planning to use TSV technology,” said Nobukazu Dejima, president of DISCO HI-TEC America, Inc. “The capability to validate complete process flows using thinned wafers at our Santa Clara research laboratory and Applied's Maydan Technology Center gives us a unique opportunity to exploit the advantages of thinned wafers in multiple TSV integration schemes.”
“We're pleased to work with DISCO to advance this exciting and disruptive technology,” said Hans Stork, group vice president and chief technology officer of Applied's Silicon Systems Group. “Our strategy to collaborate with DISCO and other leading equipment suppliers is an innovative way of doing business that can deliver robust solutions to mitigate our customers' risk and lower the overall cost of device fabrication on ultra-thin substrates.”
Through-silicon via technology is a new method that enables higher density, lower-power devices in a smaller footprint by vertically stacking chips. To make this 3-D stack, each chip or wafer layer must be reduced in thickness by up to 90% and bonded to a temporary carrier in order to maintain structural integrity during the thermal and mechanical stresses of semiconductor processing.
Combining DISCO's precision grinding equipment with Applied's etch, dielectric deposition, physical vapor deposition and chemical mechanical planarization systems, the two companies expect to develop wafer thinning and post-thinning processes of wafers bonded to silicon and glass carriers. Some of the key technical requirements in developing manufacturing-worthy equipment and process solutions are wafer structural and edge integrity, handling, dimensional control, particle control, stress management and thermal profile control.
“The alliance of Applied's process integration expertise and our leading wafer thinning systems is great news for chipmakers planning to use TSV technology,” said Nobukazu Dejima, president of DISCO HI-TEC America, Inc. “The capability to validate complete process flows using thinned wafers at our Santa Clara research laboratory and Applied's Maydan Technology Center gives us a unique opportunity to exploit the advantages of thinned wafers in multiple TSV integration schemes.”
“We're pleased to work with DISCO to advance this exciting and disruptive technology,” said Hans Stork, group vice president and chief technology officer of Applied's Silicon Systems Group. “Our strategy to collaborate with DISCO and other leading equipment suppliers is an innovative way of doing business that can deliver robust solutions to mitigate our customers' risk and lower the overall cost of device fabrication on ultra-thin substrates.”
